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Director, SOC (Frontend)

Ambiq Micro
Full-time
On-site
Singapore, Singapore, Singapore
Manufacturing & Production
Full-time
Description

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit www.ambiq.com.

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here.


Scope

As the Job Title at Ambiq, you will drive the frontend design that includes Microarchitecture, RTL design and Design Verification. In addition, in this role, will interact with customers as needed. 

This role will work with the global SOC team as well as with the Architecture, Software, PostSilicon and customer facing teams.

The successful candidate would have demonstrated ability to manage a similar team as well as having hands-on experience in these teams. The candidate demonstrates a quality and goal oriented execution with exceptional ability to communicate with the global team. 


The person in this role will build front end design capability in Singapore and expand to drive a full SOC design (RTL/DV and other functions). The front end design capability includes microarchitecture, RTL design, Design verification including gate level simulations, IO timing of various interfaces etc. 


Responsibilities

  • Responsible for high quality, on-time tapeouts with good influencing, driving collaboration skills.
  • Drive Interlock meeting between functions. Collaborate closely with Arch, SW, validation and product/application teams. 
  • Attract and retain a world class team of RTL and DV engineers.  Define team objectives and outcomes; enable success across boundaries; Help the team adapt and learn
  • Have keen eye to details across various chip design & implementation functions.
  • Budget & Resource management working with functional leads and exec management.
  • Keen in establishing processes and automation that ensures quality and enable reliable tapeouts
  • Support SOC Design, Physical Design, Design Verification, Post-Si org.
  • Track Design Metrics etc and generate relevant data for SoC org for tracking purposes.
  • Drive Lesson Learnt for SOC org and drive closure of action items
  • Schedule different design reviews (HLDR, MLDR, LLDR etc)
  • Goals tracking for team: Tracking and reporting Goals
  • Interact and support customers as needed to debug any issues or product presentations
Requirements
  • Education Requirements: Minimum requirement for this position is Bachelors in EE or CS.
  • Must have overall 15+ year of experience in the Chip Design and Management. Preferably having experience in Microarchitecture, RTL design, DV and Chip Program Management
  • Have worked in end to end of SoC design to tapeout experience.
  • Should be familiar with Design EDA tools for Synthesis, power (CLP), Constraints Verification.
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