Design general purpose I/O
include failsafe feature; Design high speed I/O, including impedance
control, slew rate control, with optimization of power, area, and meeting
high speed, good signal integrity, EMI, and ESD performance.
Plan and supervise layout, plan
and perform silicon engineering validation of I/O circuit and perform
silicon debug. Work with test engineer to plan and determine ATE test plan
for the I/O circuit.
Requirements
BS degree in electrical
engineering with 8 years of experience or more, Master degree in in
electrical engineering with 5 years of experience or more.
Strong experience and knowledge
in general purpose I/O design as well as high speed I/O design
Solid understanding of analog
design fundamentals including device physics, good circuit analytical
skill
Good experience and knowledge in
signal integrity, ESD, latch-up, EMI, and circuit design considerations
for reliability
Strong experience and knowledge
in the field of ESD is preferred
Familiar with both schematic and
layout tool, methodologies, flow and CAD tools such as SPICE, Cadence
virtuoso, Spectre, PCELL layout, Calibrephysical verification
Good team work, responsible, good
communication skill