Responsibilities:
Soc Level Backend engineer:
• Collaborate with cross-functional teams to understand backend design requirements and constraints.
• Execute backend physical design tasks, including floorplanning, SOC level place and route, power planning, and chip assembly.
• Implement and optimize physical designs for timing, area, power, and signal integrity.
• Conduct physical verification checks and address design-related issues.
• Work closely with RTL design, synthesis, and DFT teams to achieve backend design goals.
• Utilize advanced EDA tools and methodologies for backend physical design tasks.
• Contribute to the development and enhancement of backend physical design methodologies.
Requirements
Requirements:
• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of proven experience in backend physical design.
• Proficiency in industry-standard EDA tools for backend physical design and verification.
• In-depth understanding of deep sub-micron semiconductor processes.
• Strong knowledge of low power design techniques.
• Experience with place and route, clock tree synthesis, and signal integrity analysis.
• Excellent problem-solving skills and meticulous attention to detail.
• Chinese proficiency is a must for cross-country collaboration