Timing Lead Engineer

Company Overview

Ambiq's mission is to develop the lowest-power semiconductor solutions to enable intelligent devices everywhere by developing the lowest-power semiconductor solutions to drive a more energy-efficient, sustainable, and data-driven world. Ambiq has helped leading manufacturers worldwide develop products that last weeks on a single charge (rather than days), while delivering a maximum feature set in compact industrial designs. Ambiq's goal is to take Artificial Intelligence (AI) where it has never gone before in mobile and portable devices, using Ambiq's advanced ultra-low power system on chip (SoC) solutions. Ambiq has shipped more than 250 million units by 2024. For more information, visit?www.ambiq.com. 

Our innovative and fast-moving teams of research, development, production, marketing, sales, and operations are spread across several continents, including the US (Austin and San Jose), Taiwan (Hsinchu), China (Shenzhen and Shanghai), Japan (Tokyo), and Singapore. We value continued technology innovation, fanatical attention to customer needs, collaborative decision-making, and enthusiasm for energy efficiency. We embrace candidates who also share these same values. The successful candidate must be self-motivated, creative, and comfortable learning and driving exciting new technologies. We encourage and nurture an environment for growth and opportunities to work on complex, engaging, and challenging projects that will create a lasting impact. Join us on our quest for 100 billion devices. The endpoint intelligence revolution starts here. 

Scope

The Timing Lead Engineer will plan and lead timing-related activities for Ambiq’s next-generation technology development. This will include defining signoff criteria, analyzing, developing design methodology, and managing tape-outs day-to-day driven by Ambiq’s Advanced Development team. The lead will work closely with other members of the Advanced Development team and the broader engineering community at Ambiq to develop and deploy Timing signoff-related flows and methodologies to support production chip development.

The successful candidate will be comfortable working both independently and in a leadership position, collaborating with a variety of senior engineers. The successful candidate will also be comfortable with the uncertainty of new methodology development and have a strong sense of independent drive.

Specific Responsibilities

• Define and own SoC timing signoff criteria, process corners, derates, uncertainties, and their tradeoffs. Be responsible for delivering system-on-chip (SoC) Full-Chip Static Timing Analysis.
• Define and own full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoCs. Drive clock tree planning and implementation for SoCs to achieve best energy, performance, and area.
• Be responsible for synthesis, PI, reliability signoff and ESD analysis, drive feedback, and recommend design solutions. Work with product development teams to rapidly deploy timing related methods in products. 
• Plan and lead timing and other related activities for test chips owned by the Advanced Development team. As part of this effort, lead a small group of internal and/or contract resources.
• Maintain a relationship with and collaborate with 3rd party CAD tool vendors and fab during the development of new flows and methodologies. Validate and refine new techniques as part of a team that is building complex test chips in advanced FinFET nodes.

• A bachelor’s or master’s degree in electrical engineering or a related field is required. 
• Minimum 10 years of experience of hands-on experience in Static Timing Analysis, flows and methodologies for timing closure and have a strong understanding of noise, crosstalk, and OCV effects, aging, HTOL, soft errors in advanced FinFET nodes (16nm, 12nm, 7nm, 5nm)
• Proficient in Synthesis, place and route, UPF, Power integrity and reliability signoffs. Familiar with circuit modeling, including SPICE models, and worst-case corner selection.
• Experience with large design STA and Timing Closure. Familiar with ECO techniques and implementation. Experience with STA signoff constraint authoring for full-chip level, tape-out signoff requirements, checklists, and associated automation.
• Experience in Cadence EDA tools (e.g., Genus, Innovus Tempus).
• Experience developing new technologies and transitioning those technologies to production is highly desirable. Familiar with important aspects of timing of SoC designs in bulk and FinFET technologies.
• Good programming skills with Perl and TCL.